Heterojunction Negative-Capacitance Tunnel-FET as a Promising Candidate for Sub-0.4V VDD Digital Logic Circuits

The objective of this paper is to exemplify the significant improvements achieved in speed and power-consumption by utilizing negative-capacitance Tunnel FETs in sub-0.4 V _DD digital logic applications. A heterojunction negative-capacitance TFET (NCTFET) has been designed using SILVACO TCAD and its accuracy demonstrated by properly fitting the simulated polarization data with calculated L-K equation solution. The prospects of the proposed structure have been manifested in the steep average subthreshold-slope of 27mV/decade over 9 decades of current and high I _ON /I _OFF of 10 ¹⁶ , possible due to the internal voltage amplification and voltage pinning effects. The device has been suitably implemented in inverter, ring-oscillator, 2:1 multiplexer and Full-Adder circuits and benchmarked in delay and power-consumption with a reference TFET (R-TFET) and previously proposed structures. The effect of varying thickness of ferroelectric material on the circuit-level performance has also been discussed. Furthermore, the NCTFET has been implemented in a 6-T SRAM which successfully demonstrates the effect of t _FE on noise margin and read-write delay, operated at 0.4 V _DD . The proposed NCTFET has been presented and justified as a promising candidate for high-speed and low power digital circuits.