现场可编程门阵列
计算机科学
定向梯度直方图
支持向量机
管道(软件)
算法
特征提取
直方图
行人检测
块(置换群论)
计算
人工智能
计算机硬件
工程类
几何学
数学
图像(数学)
程序设计语言
行人
运输工程
作者
Pengcheng Dai,Jun Tang,Jiangnan Yuan,Yue Yu
标识
DOI:10.1109/isceic53685.2021.00037
摘要
Recently, pedestrian detection has been an important issue in the field of computer vision. To solve the problem of large computation and poor real-time performance in pedestrian detection scene of original histogram of oriented gradients (HOG) algorithm, this paper presents a simplified HOG feature extraction algorithm and an efficient architecture in field programmable gate array (FPGA). This simplified algorithm and Support vector machine (SVM) classifier are successfully implemented on Xilinx Zynq FPGA by using parallelism and pipeline technology. In the feature extraction step, the dimension of HOG feature is reduced by changing the strides of the sliding block, and the complexity of this algorithm and the utilization of hardware resources are reduced. The result shows that this proposed algorithm can achieve 86% true positive rate and 88% precision rate in training stage on INRIA and MIT datasets. The FPGA implementation with pipeline technical and parallel circuit architecture can achieve real-time detect and the simplified algorithm can greatly reduce the utilization of FPGA resources.
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