逐次逼近ADC
计算机科学
采样(信号处理)
电容器
电子工程
无线电频率
模数转换器
功率(物理)
电气工程
电压
工程类
电信
物理
探测器
量子力学
作者
Amitesh Kumar Tripathi
出处
期刊:2021 2nd International Conference on Range Technology (ICORT)
日期:2021-08-05
标识
DOI:10.1109/icort52730.2021.9581884
摘要
Direct RF sampling receivers demand an ADC which digitized several GHz signals with the highest possible spectral purity and power efficiency. Successive approximation register (SAR) is the most popular analog to digital converter (ADC) architecture for low-speed and medium resolution. Mostly digital implementation of the SAR ADC achieves the most power efficiency and consumes the least silicon area. Due to the binary search algorithm, SAR ADC suffers from speed limitations. Charge re-distribution architecture requires a large capacitor ratio which limits the resolution. This paper presents the design considerations and possible architectures for implementations of high-speed, high-resolution, and low power SAR ADC for direct RF sampling applications and proposes a 12-bit 6-GS/s pipelined SAR hybrid ADC intended for Direct RF Sampling Receivers.
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