A Design of Whole-chip ESD Protection Circuit with SCR-based I/O and LIGBT-based Power Clamp

This study proposed and fabricated an all-directional whole-chip electrostatic discharge (ESD) protection circuit design, including input/output (I/O) and power clamps. The proposed I/O ESD clamp is based on silicon controlled rectifiers (SCR) and possesses improved snapback and bidirectional characteristics owing to the insertion of an improved floating region. The proposed ESD power clamp has an excellent clamping ability and a high holding voltage owing to the use of a lateral insulated gate bipolar transistor (LIGBT). The ESD protection circuit is fabricated using a 0.18 ㎛ bipolar-CMOSDMOS (BCD) process and is properly placed in the ESD clamp position. Consequently, the proposed ESD protection circuit contributes toward improving the area efficiency and reliability of the integrated circuit. The electrical properties and robustness were analyzed using a transmission line pulse (TLP) system and an ESD pulse generator. According to the measurements, the proposed whole-chip ESD protection circuit is robust enough to discharge 8 ㎸ HBM and 800 V MM in four ESD stress modes for the input and output units (PD: positive -VDD, ND: negative -VDD, PS: positive -VSS, and NS: negative -VSS) as well as in the DS (VDD to VSS) mode between VDD and VSS.