无杂散动态范围
CMOS芯片
比较器
逐次逼近ADC
线性
电子工程
抖动
动态范围
放大器
模数转换器
计算机科学
电气工程
噪声整形
工程类
电压
作者
Yanhua Zhang,Lijie Yang,Ruirui Dang,Zhiwei Xu,Chunyi Song
标识
DOI:10.1109/cirsyssim.2018.8525871
摘要
A 14-bit 500-MS/s SHA-less pipelined Analog-to-Digital Converter (ADC) for receiver application is fabricated on a 65 nm CMOS relying on correlation-based background calibrations to correct the inter-stage gain and settling errors. In order to suppress the non-linearity caused by inter-stage gain error due to insufficient amplifier gain, a new dithering technique is employed on the residual transfer function. In addition, the comparators in all stages are trimmed digitally to minimize their offset and further improve the linearity. The measured signal-to-noise ratio (SNR) and spurious free dynamic range (SFDR) are 67 dB and 88 dB after calibration at 350 MHz input signal. The ADC occupies an active area of 3 mm2 and consumes a total power of 0.9 W from 1.3 V and 2.0 V supplies.
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