Enabling 3D NAND bit cost scaling with merged etches

Abstract High aspect ratio (AR) etches play a critical role in defining 3D NAND memory devices. As 3D NAND devices scale predominantly in the z direction, AR dependent etching becomes a major limiting factor in cost scaling. In this work, deposition and etch process development understanding combined with integration and feature scale modeling is applied to cost-effectively merge etches with minimal downstream device impact. Merged SiO 2 /Si 3 N 4 (ONON) memory channel and SiO 2 interlayer dielectric (ILD) contact etch was achieved by doping the ILD to enable SiO x contact etch depth and profile control while maintaining the same memory channel cryo etch process. Furthermore, co-doping the SiO x ILD layer shows high etch rates while enabling profile control through etch byproduct redeposition management. In addition, co-doping minimizes downstream integration impact and device properties based on hot phosphoric wet etch rate and blanket oxide leakage current measurements, respectively.