Numerical Simulations of IBC Solar Cells Based on Poly-Si Carrier-Selective Passivating Contacts

量子隧道 钝化 光电子学 共发射极 材料科学 量子效率 硅 计算机科学 载流子寿命 拓扑(电路) 电子工程 物理 图层(电子) 电气工程 纳米技术 工程类
作者
Paul Prócel,Guangtao Yang,Olindo Isabella,Miro Zeman
出处
期刊:IEEE Journal of Photovoltaics [Institute of Electrical and Electronics Engineers]
卷期号:9 (2): 374-384 被引量:25
标识
DOI:10.1109/jphotov.2019.2892527
摘要

This paper presents an analysis of physical mechanisms related to operation and optimization of interdigitated back contact (IBC) poly-silicon-based devices. Concepts of carrier selectivity and tunneling are used to identify the parameters that impact on the fill factor. Then, based on technology computer-aided design (TCAD) numerical simulations, we describe the device performance in terms of transport and passivation. A validation of the model is performed by matching measured and simulated R, T, and external quantum efficiency spectra and electrical parameters. As result of such process, the opto-electrical losses of the reference device are identified. Then, we execute a study of the impact of process parameters on the performance of the IBC device under analysis. Assuming a uniform SiO 2 layer, simulation results reveal that both n-type and p-type poly-Si contacts can be theoretically perfect (i.e., approx. lossless), if assuming no interface recombination but considering tunneling of both carrier types. In other words, there exists an optimum oxide thickness (1 nm) for which majority carriers tunneling works already very well, and minority tunneling is still low enough to not result in significant recombination. Moreover, SiO 2 thickness up to maximum 1.6 nm is crucial to achieve high efficiency. Regarding rear geometry analysis, the efficiency curve as a function of emitter width peaks at 70% of pitch coverage. Further, it is shown that diffused dopants inside crystalline silicon make the device resilient to passivation quality. Finally, the calibrated model is used to perform an optimization study aiming at calculating the performance limit. The estimated performance limit is 27.3% for a 100-μm-thick bulk, 20-nm-thick poly-silicon layers, silver as rear contact, and double ARC.
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