NMOS逻辑
德拉姆
材料科学
金属浇口
光电子学
锡
制作
逻辑门
静态随机存取存储器
节点(物理)
电子线路
堆栈(抽象数据类型)
电气工程
电子工程
栅氧化层
电压
晶体管
计算机科学
工程类
冶金
医学
替代医学
结构工程
病理
程序设计语言
作者
E. Capogreco,Hiroaki Arimura,R. Ritzenthaler,S. Brus,Yusuke Oniki,Emmanuel Dupuy,Farid Sebaai,D. Radisic,Boon Teik Chan,Dong Zhou,Vladimir Machkaoutsan,S. Yoon,H. Itokawa,M. Yamaguchi,Zheng Gao,P. Fazan,Y. Chen,S. Subramanian,Lars‐Åke Ragnarsson,A. Spessot
标识
DOI:10.1109/iedm45625.2022.10019422
摘要
In this work, a 14-nm-node Replacement Metal Gate (RMG or "Gate Last") high-k Last FinFET flow, compatible with the high thermal budget required during a DRAM fabrication process is demonstrated for the first time, with proven functionality of SRAM and Ring Oscillators. An extensive analysis is conducted for the assessment and optimization of the nMOS gate stack. A thermally stable nMOS gate stack featuring Lanthanum (La)-dipole and TiN/TiAl/TiN Work Function Metals (WFMs) is proposed to achieve sub 0.2 V nMOS threshold voltage $(V_{t})$.
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