Toward a High-Performance and Low-Loss Clos–Benes-Based Optical Network-on-Chip Architecture

As chip multiprocessors (CMPs) keep growing in capability, on-chip communication efficiency is crucial to the overall performance. However, on-chip networks based on electronic switches suffer from excessive power consumption and limited performance. In order to take advantages of optical interconnect, we propose an optimized design toward a high-performance and low-loss Clos-Benes-based hierarchical optical network-on-chip (NoC) for large-scale CMPs. We propose several key techniques, including a loss-aware adaptive (LAA) routing for intraswitch Benes network, a priority-based round-Robin virtual output queue selection and a Q-learning-based heuristic routing for interswitch Clos network, and a local transfer link (LTL) technique to improve the traffic locality. A case study on a 256-core CMP under uniform traffic shows that the network throughput is increased by 346.7%, 61%, and 12.9%, respectively, than the mesh, fat-tree, and the traditional generic Clos-Benes optical NoC. On average of a set of real applications, the application end-to-end delay is reduced by 47.6%, 28.2%, and 19.4%, respectively, than the mesh, fattree, and the traditional generic Clos-Benes network. Meanwhile, the average optical power loss is decreased by 11.8% and 49.9%, respectively, as compared to the mesh and fattree. As compared to a baseline Clos-Benes network, the use of LAA routing together with the LTL could reduce the average optical power loss by 28.4%.