Analysis and Design of a 500-kS/s Zoom-Based Second-Order-to-Exponential Incremental ADC Using Noise-Coupling-Assisted Summer

This paper presents a zoom-based discrete-time (DT) incremental ADC (IADC), where the fine ADC works as a$2^{\mathrm {nd}}$-order IADC in the$1^{\mathrm {st}}$step, while it switches to a pure exponential IADC in the$2^{\mathrm {nd}}$step. To avoid hardware redundancy, the fine IADC reuses a single noise-coupling (NC)-assisted summer across both conversion steps. In the$1^{\mathrm {st}}$step, the summer cascades with a single integrator to form a$2^{\mathrm {nd}}$-order delta-sigma loop for 125 cycles. Subsequently, it is reconfigured for a 3-cycle exponential extended counting (EEC) operation by disconnecting the input and integrator, while adjusting the NC feedback gain from unity to two. This two-step architecture improves accumulation efficiency while exhibiting lower sensitivity to coefficient errors during the EEC operation. Thanks to the zoom structure, the 5-bit coarse SAR ADC confines the residual signal amplitude, thereby reducing the internal signal swing of the fine IADC, especially at the NC-assisted summer output. As a result, it enables the use of a 1.5-bit quantizer (QTZ) in the fine IADC, thus significantly simplifying the quantization and the NC implementation in the$2^{\mathrm {nd}}$stage. Prototyped in a 65-nm CMOS process, operating at 64 MHz, it achieves a signal-to-noise and distortion ratio (SNDR) and dynamic range (DR) of 88.7dB and 93.0dB over a 250-kHz bandwidth. Supplied at 1.2V, it consumes 2.9mW, resulting in a$\mathrm{FoM}_{\mathrm {S\vert DR}}$of 172.4dB.