PMOS逻辑
NMOS逻辑
可靠性(半导体)
材料科学
负偏压温度不稳定性
光电子学
MOSFET
电气工程
物理
电压
晶体管
工程类
热力学
功率(物理)
作者
Wen‐Shiang Liao,Yie-Gie Liaw,Mao-Chyuan Tang,Sandipan Chakraborty,C. W. Liu
标识
DOI:10.1109/led.2008.2000723
摘要
Three-dimensional vertical double-gate (FinFET) devices with a high aspect ratio (Si-fin height/width = H fin /W fin = 86 nm/17 nm) and a gate nitrided oxide of 14 Aring thickness have been successfully fabricated. Reliability characterizations, including hot-carrier injection (HCI) for NMOS FinFETs and negative bias temperature instability (NBTI) for PMOS FinFETs, are carried out in order to determine their respective lifetimes. The predicted HCI dc lifetime for a 50-nm gate-length NMOS FinFET device at the normal operating voltage (V cc ) of 1.1 V is 133 years. A wider fin-width (27 nm) PMOS FinFET exhibits promising NBTI lifetime such as 26.84 years operating at V cc = 1.1 V, whereas lifetime is degraded for a narrower fin-width (17 nm) device that yields 2.76 years of lifetime at the same operating voltage and stress conditions.
科研通智能强力驱动
Strongly Powered by AbleSci AI