Transient self back-biased buffer for low-voltage high-performance applications in standard CMOS technologies

A low-voltage, high performance buffer suitable for implementation in standard CMOS technologies is proposed. The new buffer utilises the transient self back-bias (TSBB) technique to reduce electrically the threshold voltage of the output PMOS transistor, enhancing its performance. Simulations at 100 MHz and 0.9 V have shown that the TSBB buffer has a 35% speed advantage in the pull-up over the standard CMOS buffer, with only 5% increase in power dissipation.