A 0.69-Noise-Efficiency-Factor 4 x-Current-Reuse Dynamic Comparator with A Stacking FIA

Comparator is a connection between the analog and digital worlds [1] –[5]. A low-noise and low-power comparator is important in many applications, such as SAR ADC. Traditionally, such a comparator is realized as the Strong-Arm (SA) latch. It has the advantage of fullydynamic operation and embedded pre-amplifier. However, its preamplifier gain is as low as 4 5, which increases the input-referred noise and offset. In recent years, there are many efforts to design a more efficient dynamic comparator. Both [1] and [2] improve the dynamic-bias comparator of [3] that is based on the subthreshold-biased input transistors for large $\mathrm{g}_{\mathrm{m}} / \mathrm{l}_{\mathrm{D}}$. Among them, [1] uses a floating inverter amplifier (FIA) as the pre-amplifier. This pre-amplifier has a large voltage gain of approximately 30, which suppresses the noise and offset effectively. It realizes a 2-times current reuse, improving the energy efficiency. However, the energy efficiency can hardly be improved further, since it is independent of the device sizes. The current reuse is also limited to 2 times, which is far away from the maximum possible times (for example, 4 times in this work). [2] uses a charge pump and capacitive positive feedback for faster speed but at the cost of increased power. Its noise is also as large as $174 \mu \mathrm{V} \mathrm{rms}$, which is 3.8 times larger than [1].