Research on Silicon Wafer Surface Phase Under Ultra-Thin Slicing Process and its Etching Hindrance Behavior During Metal-Assisted Chemical Etching

To achieve high-efficiency and low-cost solar cells, ultra-thin silicon slicing technology is critically important in Photovoltaic (PV) industry. However, the surface phase evolution of silicon wafers under ultra-thin slicing process and resulted etching behavior remain unclear. In this study, the surface phase evolution of different thickness silicon wafer surface has been carefully studied. As the thickness of silicon wafers became relatively thin, the degree of surface stress-induced amorphous silicon (ST-α-Si) has been found greatly increase. Moreover, the UPS test showed the ST-α-Si layer has an orbital energy level much lower than that in monocrystalline silicon thereby having lower reduction performance during MACE. A copper deposition experiment was conducted to study the etching hinder behavior effect caused by silicon surface ST-α-Si phases. It showed that the presence of ST-α-Si adversely affected copper deposition. To improve the MACE uniformity, a pretreatment using HF/H2O2 mixed solution to remove the surface ST-α-Si layer has also been investigated. After HF/H2O2 pretreatment, the uniformity of MACE formed inverted pyramids in silicon wafer surface has been significantly improved. Moreover, the reflectance of MACE textured surface has been further reduced down to 7.67% from 10.10 % compared that without pretreatment.