A Switching NMOS Based Single Ended Sense Amplifier for High Density SRAM Applications

The demand for single ended static random access memory is growing, driven by the decreasing technology node and increasing processing load. This mandates the need for a single ended sense amplifier to be used along with the memory. Consequently, a single ended latch based sense amplifier is proposed in this article for high-speed, low power application. The sense amplifier is designed at a 32 nm technology node and its functioning is analyzed at 1 V supply voltage, while the environment temperature is maintained at 27 °C. It is analyzed for its delay, temperature tolerance, variability tolerance, and area occupancy. The delay requirement of 0.2 ns for the proposed scheme is significantly lower in comparison to its other counter parts. While, its false read time is 0.3μs. In terms of power consumption, the proposed sensing topology is marginally higher than SPSS, but its leakage power is 1.4 times less than SPSS. The major advantage of the proposed SA is its reduced area footprint of 7.65 μm 2 , which is 1.78 times better than the best pre-existing topology in terms of area.