Module-level material engineering for continued DRAM scaling

Memory-hungry applications in the current data-driven economy demands DRAM devices with higher bit densities at a low cost. This demand has driven DRAM manufacturers to find innovative methods to extend Moore's scaling and reduce the area required to store individual bits. A DRAM unit memory cell is based on a one transistor one capacitor (1T1C) design. To increase DRAM densities, both transistor and capacitor must scale. As the capacitor diameter shrinks with scaling, the ratio of its height to its diameter--its aspect ratio (AR)--climbs quickly. This higher AR results in the need to produce relatively deeper holes to fabricate capacitors, increasing the demands on etch and deposition processes. In this paper, we present a solution to capacitor scaling by co-optimization of the hardmask and etch. The co-optimization involved novel deposition and etch techniques to enable continued scaling while maintaining device performance. We also discuss novel metrology methods that enable us to test and optimize the unit processes as well as the module-level integrated sequence.