Warpage Analysis and Optimization of Fan-Out Panel-Level Packaging with Chip-Last Process

Electronic products are evolving toward miniaturization, high integration, and low prices, which requires us to improve production efficiency, reduce costs, and increase their high integration while ensuring the yield rate. Fan-Out Panel-Level Packaging (FOPLP) technology is meeting market requirements. However, warpage due to the shrinkage of the epoxy molding compound (EMC) during the post-curing stage and the mismatch in the coefficients of thermal expansion (CTE) of the individual encapsulation materials is an important issue in the production and application of this technology. Therefore, it is important to simulate and optimize the warpage of FOPLP before production and processing.In this paper, regarding the manufacturing process of "Chip Last", the warpage of FOPLP in the post-curing stage is predicted by using finite element simulation. The equivalent parameter method is used to calculate the material parameters of the RDL layer, and increasing stress relief groove on the EMC, established a proportional reduction model of the structure of "EMC-Chip-Temporary bonding layer-RDL-Carrier", to study the factors that affect warpage and stress in the post-curing stage of large panel-level fan-out packaging. The effects of material characteristics (CTE, Young's modulus), the proportion of copper volume in RDL, and stress relief groove on warpage were studied by controlling variable method. Experimental results show that Stress release grooves can reduce warping and thermal stress, and better optimization results can be obtained by changing the depth, width, and the total number of arrays of the groove structure. Increasing the volume fraction of copper in RDL or choosing materials with similar CTE can also reduce the warpage. This conclusion can be used to predict and improve plate-level warping by material selection before process production, and help to rationalize the package structure design to reduce warping.