Advanced Flip Chip Packaging

Flip Chip (FC) technology has been introduced for over 50 years (by IBM in the early 1960s), which is widely used for electronic packaging due to some benefits like smaller form factor, higher UPH (Units Per Hours), direct thermal dissipation path and good electronic performance. With the continued downscaling of device transistor dimension followed by the shrunk interconnection pitch, there are various interconnection types used in flip chip packages are also continuously developed for better reliability performance. As of now, these types have an evolution from C4 (Controlled Collapse of Chip Connection) to Cu pillar and further to micro-Cu pillar bumps. In general, flip chip interconnection using solder bump has an excellent yield due to the self-alignment characteristic of solder material. However, its high solder volume gives some design limitations and consideration for its reliability performance. From assembly perspective, the C4 interconnection with narrower pitch design is not recommended due to the larger space needed for the spherical solder ball, high bridging risk and the concern on effective current-flow path, which lead to Cu pillar bumps become the mainstream of a first-level, advanced FC package interconnect. Furthermore, the micro-Cu pillar bump (or called micro bump) for advanced interconnection pitch required for heterogeneous integration such as GPU (Graphics Processing Unit) and HBM (High Bandwidth Memory) in 2.5D packages, have been already applied for over 10 years. This Chapter will introduce these flip chip packaging technology, the relative assembly processes and the reliability challenges for memory relative packages.