Optimization of UART Communication Protocol Based on Frequency Multiplier Sampling Technology and Asynchronous FIFO

Universal Asynchronous Receiver/Transmitter, commonly known as UART, is a serial, asynchronous, full-duplex communication protocol, which is widely used in the embedded field based on this protocol, this paper uses Verilog HDL Designed and improved on traditional methods. The design of the UART receiver module and UART transmitter module and the corresponding improvement methods are discussed emphatically. The core problems of improvement are as follows. 1)This paper uses the isolation characteristics of asynchronous FIFO to avoid the complexity of design and constraints caused by transmission across clock domains. It is solved the problems that the data transmission data belongs to different clock domains and different transmission rates, and the width of the data interface is different. 2)This paper creates a data buffer to address the issue that, if the device is out of sync, the remaining data would be lost or rewritten because of the time difference between the transmitting and receiving ends. 3)This paper establishes a communication network control system model, uses the previous buffer to fix the delay time, and solves the optimal sampling times and upper limit of each data bit, avoiding the large delay of the signal in the system. 4)This paper uses the optimal frequency multiplication sampling technology to improve the receiving accuracy of the receiver and avoids the problem of decreasing the transmission efficiency between devices by adding multiple cycles to each round of oversampling. Finally, the designed and improved UART protocol has passed all functional simulations in Modalism SE-64 and is superior to the traditional method in many aspects such as transmission efficiency, bit error rate, and anti-interference.