Analysis of On-Chip Inductors and Arithmetic Circuits in the Context of High Performance Computing

The increase in computing performance of integrated circuits over the last decades through shrinking transistor and interconnect sizes by several orders of magnitude has enabled many technological advancements. Today the design of high performance computing (HPC) systems is mainly limited by two major factors: I/O-bandwidth and power consumption. This work takes an in-depth view on one aspect of each of those limitations. Firstly, the I/O-bandwidth is addressed with an analysis of on-chip inductors for high-speed SerDes designs. Secondly, the design of arithmetic circuits for addition, multiplication, and floating-point computation is analyzed. \nWhile the on-chip structures have scaled down extremely, the pin count of packages could not be increased accordingly, which is known as pin limitation. Thus, I/O cells are required to increase the bandwidth per pin to serialize the parallel data for transmission. Such SerDes have to cope with signal degradation caused by channels for multi-gigahertz signals by employing dedicated circuits. This includes an adequate signal termination, which is however compromised by the parasitic capacitance of the electrostatic discharge protection. This work analyzes how the capacitance can be compensated with on-chip inductors to reduce reflections back into the channel. \nUnlike other devices, on-chip inductors are rarely provided by process design kits (PDKs) so layout and modeling has to be done by the designer. This work presents an evaluation of different methods for parameterized cells for inductors. The background on analytical inductance calculations is researched and different approximations of the mean distance formula found in literature are compared. A new expression for the internal inductance of straight wires is derived. The influence of oxide and substrate, skin effect, metal fill, and process corners is analyzed. Inductor simulation with field solvers and associated problems are presented. This work closes the gap between simulated S-parameters and lumped models used in circuit design with a Markov-Chain Monte-Carlo fitting technique. Using these results, it is shown how a lumped model can be expressed in terms of layout geometry, similar to what is commonly available for PDK devices. The result is accurate enough to be used for circuit optimization. \nThe processors used in data-centers, HPC systems, and many other devices are almost exclusively proprietary designs from established companies with instruction set architectures (ISAs) associated with high licensing costs. In 2010, the open-standard RISC-V ISA was released by the University of California, Berkeley, and has obtained great momentum in the last few years. It is said to start a "new era of computer architecture" as many companies and universities start to develop - often small - custom RISC-V cores. It is crucial to include very fast arithmetic units into such cores for RISC-V to enter the HPC environment. \nTherefore, this work analyzes an IEEE 754 floating-point unit for fused multiply-add operations developed at the Computer Architecture Group at Heidelberg University. Design, verification, and a power-performance-area (PPA) analysis are presented. Comparable designs available in the open-source space tend to prefer high-level descriptions of multiplication and addition. This work investigates if there are potential gains in PPA that can be achieved through gate-level implementations of arithmetic circuits. However, the results strongly suggest that modern back-end tools are perfectly capable to outperform custom structures and design effort should be directed towards other aspects.