Warpage Measurements and Characterizations of Fan-Out Wafer-Level Packaging With Large Chips and Multiple Redistributed Layers

In this paper, the warpages of a chip-first and die face-up fan-out wafer-level packaging (FOWLP) with a very large silicon chip (10 mm × 10 mm × 0.15 mm) and three redistributed layers are measured and characterized. Emphasis is placed on the measurement and 3-D finite-element simulation of the warpages during the FOWLP fabrication processes, especially for: 1) right after postmold cure; 2) right after backgrinding of the epoxy molding compound to expose the Cu-contact pads; and 3) the individual package (right after the solder ball mounting and dicing) versus surface mount technology reflow temperatures. The simulation results are compared to the measurement results. Some recommendations on controlling the warpages are provided.