Transistor Reliability Characterization for Advanced DRAM with HK+MG & EUV process technology

With the growth of high performance computing on many industrial sectors that includes mobile/network and data centers/servers, the need for continued technology scaling and advancements on new process technology have paved ways to manufacture advanced semiconductor products. High-k + Metal gate devices and most recently EUV lithography process have become a key enabler for the 7nm technology nodes and beyond [1]. These technologies are being adopted in the advanced DRAM nodes. DRAM memory uses various devices such as MOSFETs (w/ and w/o HK+MG), cell transistor, cell capacitor, and its reliability has also been considered according to the designed purposes. This paper reviews comprehensive reliability on all types of devices used at each circuit in 15nm DRAM memory. The intrinsic reliability of devices in peripheral regions was guaranteed with systematic wafer-level-reliability evaluation up to product level testing for 1000hrs. The reliability of transistors in core regions was verified using design for reliability, various test structures, and up to an accelerated product level aging test. With the suggested degradation modeling of the capacitor in cell regions, the result on 32GB DIMM field tested for over 1 years shows the best in class reliability results and meets 10yrs of lifetime.