Zigzag nanosheets transistor introduction: a path for forksheet FET architecture scalability

This paper presents a new transistor design that enables scalability of a nanosheet field effect transistor (FET) architecture. By introducing an innovative patterning design for the nanosheets (a zigzag shape), the contacted poly pitch (CPP) can be reduced to a 30nm size. Semiconductor virtual fabrication was used to create virtual prototypes of this new device architecture and evaluate different process and design assumptions.