SAR ADC Architecture with Digital Error Correction

Abstract This paper describes a high‐performance successive approximation register (SAR) analog to digital converter (ADC) using three comparators operating in parallel, instead of just one as in conventional ADCs. This comparator redundancy enables potentially faster operation, higher reliability, and comparator error correction. Reliability‐enhancement and error‐correction algorithms are described. We designed and implemented a 10‐bit, 6‐Msps SAR ADC with three comparators by using TSMC 0.18 µm CMOS technology. The advantages of high conversion rate and higher accuracy are verified by transistor‐level circuit simulation and experimental results of the test chip. Copyright © 2010 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.