Process Development of Manifold Microchannels Cooling for Embedded Silicon Fan-Out (MMC-eSiFO) Package

As Moore’s Law tends to reach its limits, shrinking process technology nodes is no longer the most effective way to improve the performance of systems, and more attention is being focused on advanced packaging. Thermal dissipation as the main issue severely limits the reliability of 3D stacked modules. Embedded cooling is a feasible solution for interlayer cooling. However, the current manifold is incompatible with advanced packaging processes due to the footprint and manufacturing process. In this work, a manifold microfluidic cooling structure for embedded silicon Fan-Out (MMC-eSiFO) package is proposed and the thermal test vehicle (TTV) is designed, fabricated and tested. A silicon-based interposer is formed using a wafer bonding process by etching a cavity structure and a manifold channel on two silicon wafers, respectively. The large-area high-power chip is embedded into the cavity for effective cooling by the embedded microchannels. A high-density redistribution layer (RDL) is used to fan out the electrical I/O after fabricating the dielectric layer on the surface. In addition, multi-layer embedded liquid cooling of 3D package structure can be achieved by interposer with through silicon vias (TSVs). The use of a silicon-based interposer not only enables high aspect ratio TSVs and high-density RDL but also helps to reduce thermal stress in the package structure, as the interposer material is the same as the IC chip material. It is worth noting that the fabrication of the interposer and fan-out layer is wafer-level processing that enables production at scale. Multiple sets of cavities and manifold channels can be etched in a single package structure, making it compatible with chiplet technology. The package structure is expected to solve the thermal dissipation problem of multi-layer multi-chip assemblies.