单层
成核
材料科学
原子层沉积
光电子学
晶体管
范德瓦尔斯力
绝缘体(电)
纳米技术
薄膜晶体管
半导体
双层
图层(电子)
自组装单层膜
薄膜
化学物理
沉积(地质)
场效应晶体管
铝
氧化铝
自组装
二硒化钨
氧化物
作者
Alexander B. Shearer,Jung-Soo Ko,Anh Tuấn Hoàng,Andreas Werbrouck,Amnon Rothman,Dea Fackovic Volcanjk,Yuan-Mau Lee,Robert K. A. Bennett,Andrew J. Mannix,Krishna C. Saraswat,Eric Pop,Stacey F. Bent
出处
期刊:ACS Nano
[American Chemical Society]
日期:2025-09-08
卷期号:19 (37): 33473-33484
被引量:2
标识
DOI:10.1021/acsnano.5c10705
摘要
Integration of ultrathin, high-quality gate insulators is critical to the success of two-dimensional (2D) semiconductor transistors in next-generation nanoelectronics. Here, we investigate the impact of atomic layer deposition (ALD) precursor choice on the nucleation and growth of insulators on monolayer MoS2. Surveying a series of aluminum (AlOx) precursors, we observe that increasing the length of the ligands reduces the nucleation delay of alumina on monolayer MoS2, a phenomenon that we attribute to improved van der Waals dispersion interactions with the 2D material. Using the precursor triisobutylaluminum (TIBA), we achieve uniform coverage of ∼3 nm AlOx on MoS2 after just 30 cycles. We also build top-gated transistors with alumina seed layers grown by different precursors, demonstrating how the nucleation behavior of the seed layer influences the device behavior. With a bilayer stack of TIBA-AlOx and HfO2 as the top-gate insulator, we achieve n-type MoS2 transistors with negligible hysteresis, small and positive threshold voltage, ∼80 mV/dec subthreshold swing at room temperature, and a top-gate equivalent oxide thickness of 0.95 nm. Through this work, we develop a simple, industry-compatible, all-ALD process for depositing a top-gate insulator directly on monolayer MoS2, and we elucidate critical insights into how the ALD chemistry can be tuned to improve insulator deposition.
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