Enabling Merged 3D NAND Memory Hole and Interlayer Dielectric (ILD) Contact Etches with Deposition and Etch Co-Optimization (DECO)

Recent advances in 3D NAND memory hole etch cryo chemistry has significantly improved etch rates and aspect ratio dependent etch (ARDE) to lower scaling costs; however, ARDE inherent in plasma etch processes cannot be eliminated. As a result, continuous co-optimized improvements in 3DNAND architecture, integration, and process innovations are needed to continue cost effective 3D NAND scaling. In this work, deposition and etch co-optimization (DECO) is explored to merge memory hole and contact etches to reduce patterning steps and costs. The interlayer dielectric oxide (ILD) is doped allowing modulation of the etch depth and profile during cryo memory hole. The doped ILD oxide wet etch properties and leakage current are also compared to a baseline ILD to ensure integration compatibility.