Design of High-Linearity Power Amplifier for Wi-Fi 6 Applications

In this paper, a CMOS power amplifier (PA) design with ultra-low Error Vector Magnitude (EVM) performance for Wi-Fi 6 applications is designed and presented. The PA design is carried out using a 40 nm CMOS process, with a center frequency of 2.442 GHz and an operational bandwidth of 400 MHz. It employs a Cascode structure combined with the current combining structure, achieving a saturated output power (Psat) of 29 dBm and a gain of 16 dB. The PA design in this paper greatly improves its EVM by using AM-AM and AM-PM distortion compensation structures. Additionally, the capacitive cross-coupling neutralization techniques are utilized to mitigate the trade-off between EVM performance and PA stability. It is found that the capacitive cross-coupling neutralization structure can also be used to reduce the AM-PM distortion that happened between gm cell and Cascode cell. As a result, this PA can achieve EVM of -48.3 dB at output power of 18dBm while maintaining stability. The SNR of PA input is set to 52 dB. The circuit structure, design method, and simulation results of this PA are presented in the paper. This PA design technology is very suitable for the design of Wi-Fi 6 transmission (TX) links.