Design methodology for broadband delta-sigma analog-to-digital converters

A systematic method for designing broadband delta-sigma modulators will be described. In particular, the design of a delta-sigma modulator in a 0.18 /spl mu/m CMOS process achieving a 13-bit resolution over a 1 MHz bandwidth is presented. Circuit non-idealities in the main building blocks are modeled in Simulink/Matlab/spl reg/ allowing one to optimize the design for power, bandwidth and resolution. Methods for enhancing the speed of optimization will be described.