电容
相关双抽样
噪音(视频)
物理
光电子学
放大器
寄生电容
材料科学
电气工程
光学
CMOS芯片
工程类
计算机科学
电极
量子力学
人工智能
图像(数学)
作者
Songlei Huang,Zhangcheng Huang,Yu Chen,Tao Li,Jiaxiong Fang
摘要
A low noise low power 512×256 readout integrated circuit (ROIC) based on Capacitance Trans-impedance Amplifier (CTIA) was designed in this paper. The ROIC with 30μm pixel-pitch and 70 fF integrated capacitance as normal structure and test structure capacitance from 5 to 60 fF, was fabricated in 0.5μm DPTM CMOS process. The results showed that output voltage was larger than 2.0V and power consumption was about 150mW, output ROIC noise was about 3.6E-4V which equivalent noise was 160e-, and the test structure noise was from 20e- to 140 e-. Compared the readout noises in Integration Then Readout (ITR) mode and Integration While Readout (IWR) mode, it indicated that in IWR mode, readout noise comes mainly from both integration capacitance and sampling capacitance, while in ITR mode, readout noise comes mostly from sampling capacitance. Finally the ROIC was flip-chip bonded with Indium bumps to extended wavelength InGaAs detectors with cutoff wavelength 2.5μm at 200K. The peak detectivity exceeded 5E11cmHz1/2/w with 70nA/cm2 dark current density at 200K.
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