放大器
逐次逼近ADC
电子工程
计算机科学
频道(广播)
CMOS芯片
材料科学
光电子学
电气工程
电信
工程类
电压
电容器
作者
Wenning Jiang,Yan Zhu,Minglei Zhang,Chi-Hang Chan,Rui P. Martins
出处
期刊:IEEE Journal of Solid-state Circuits
[Institute of Electrical and Electronics Engineers]
日期:2020-02-01
卷期号:55 (2): 322-332
被引量:27
标识
DOI:10.1109/jssc.2019.2948170
摘要
A temperature-stabilized 12-bit single-channel successive approximation register (SAR)-assisted pipelined analog-to-digital converter (ADC) running at 1 GS/s with Nyquist signal to noise and distortion ratio (SNDR) above 60 dB is presented. The ADC uses a three-stage (4 b-4 b-6 b) SAR-assisted pipeline hybrid architecture to achieve an attractive energy efficiency along with an extended sampling rate. A high-linearity open-loop Gm-R-based residue amplifier (RA) with both complete-settled and dynamic features improves the residue amplification efficiency and speed, while reducing the gain variation over a temperature drift. The inter-stage gain variation over the temperature is compensated through complementary temperature coefficients (TCs) from the inner devices of the RA. Furthermore, a cascade amplification topology in the backend RA alleviates the effect of the input parasitic capacitance to its front-end capacitor DAC (CDAC), thus leading to a small CDAC size to accelerate amplification and conversion. The prototype ADC was fabricated in a 28-nm CMOS process and consumes 7.6 mW from a 1-V power supply at 1 GS/s. The measured inter-stage gain variation is less than 2.3% with a temperature range from 0 °C to 80 °C. The SNDR and SFDR are 60 and 74.6 dB with a Nyquist input, respectively, achieving a Walden figure-of-merit (FoM) of 9.3 fJ/conversion-step and a Schreier FoM of 168.2 dB.
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