A novel 10 ps resolution TDC architecture implemented in a 130nm process FPGA

This paper presents a novel high-resolution, high-precision time-to-digital converter (TDC) architecture targeting an FPGA implementation. The proposed architecture relies on multiple parallel tapped-delay lines, taking advantage of the fast dedicated carry-chains available within modern FPGAs. Moreover, the architecture presented in this work enables to overcome resolution limitation imposed by minimal delays, providing significant resolution enchancement over the widespread single tapped-delay line architecture. A TDC with 10 ps resolution and 24 ps precision has been implemented on a 130 nm fabrication process Virtex-II Pro FPGA. The results obtained using 10 parallel tapped-delay lines, each featuring ~27 ps resolutions, show that over 5× resolution enchancement factors can be obtained over a single tapped delay line architecture.