Post-Route Performance Estimation Method for Reconfigurable Systems-on-a-Chip

The well-known methods for evaluating the performance of digital circuits designed using the Field-Programmable Gate Array (FPGA) or Reconfigurable System on a Chip (RSoC) use simplified elements delay model or the simulation of the final post-routing SPICE-netlist. SPICE simulation is highly dependent on the circuit size and the amount of used routing resources and can be time-consuming. Therefore, it's necessary to quickly evaluate the circuit performance before the verification stage using SPICE simulation. Performance evaluation is required after routing as well as at the other design stages.This article describes the developed method for the quick post-routing performance estimation. We show its necessity and present a step-by-step process of adding it in a whole RSoC design flow. This method uses software that performs static timing analysis using a characterized logic elements library in Liberty format and nets capacitive characteristics. The article also considers the advantages, limitations, problems and features of the proposed method.