Design of Majority Logic Based 4-bit Approximate Subtractors and its Application in Divider

Approximate computing is an emerging computing paradigm that enables the improvement of power, performance, and area with the relaxation of accuracy. Lots of nanotechnologies efficiently realize the majority logic function instead of the traditional AND/OR logic operations. In this paper, we propose two novel majority logic-based 4-bit approximate subtractors (MLASs), one for the accuracy-constrained logic gate optimization (MLAS1) and the other one for the best logical delay (MLAS2). The proposed designs are applied in an 8/4 unsigned restoring array divider which adopts MLASs as the building blocks. The experimental results indicate the proposed designs have a significant reduction in the number of logic gates with similar accuracy. As an example, the MLAS1-based approximate divider saves 20% majority gates and 15.4% inverters compared with a state-of-the-art design.