A Novel Hybrid CMOS-Memristor Based 2-Bit Magnitude Comparator using Memristor Ratioed Logic Universal Gate for Low Power Applications

In recent years, memristor-based digital circuit design has become one of the prime focuses for low power, area-efficient VLSI design. A comparator is a combinational circuit used in complex ALU for the comparison of n-bit numbers. The unique hybrid 2bit CMOS-based comparator with Memristor Ratioed Logic Universal Gates has been implemented in this study (MRLUG). The proposed 2-bit magnitude comparator is verified by theoretical analysis and SPICE simulations. The area on-chip and power analysis are performed and the results are compared with conventional CMOS logic and threshold logic-based magnitude comparator. The feasibility of the proposed design is analyzed using LTSPICE and simulation results show an average power consumption of $39.92\mu \mathrm{W}$ and 32.14% improvement in the area compared to resistive threshold logic (RTL).