抖动
正交(天文学)
物理
相(物质)
算法
数学
电子工程
光学
工程类
量子力学
作者
Zhaowen Wang,Yudong Zhang,Yuka Onizuka,Peter R. Kinget
出处
期刊:IEEE Journal of Solid-state Circuits
[Institute of Electrical and Electronics Engineers]
日期:2022-06-01
卷期号:57 (6): 1776-1787
被引量:6
标识
DOI:10.1109/jssc.2021.3124486
摘要
We present a high-accuracy, low-jitter, multi-phase clock generator (MPCG) based on a multi-phase, injection-locked ring oscillator (MPIL-ROSC) with a quadrature delay-locked loop (QDLL). The QDLL tunes the ring oscillator (ROSC) self-oscillation frequency ( ${f}_{{0}}$ ) and provides it with multi-phase injection signals. The proposed architecture breaks the intrinsic tradeoff between jitter and phase accuracy in two-phase injection-locked ROSCs. The MPCG’s eight-phase output clock drives a 7-bit phase interpolator (PI) for phase and frequency deskew. A 1.2-V 65-nm CMOS MPCG prototype chip has a better-than-1° eight-phase accuracy and $58.8~\mathrm {fs}_{\mathrm {rms}}$ jitter (integrated from 100 kHz to 1 GHz), while consuming 15.6 mW at 7 GHz, yielding a −252.7-dB figure of merit ( $\mathrm {FOM}_{\mathrm {jitter}}$ ). The peak-to-peak integral nonlinearity (INL) and the peak-to-peak differential nonlinearity (DNL) of the PI are less than 1.9 and 1.2 LSB, respectively, across a frequency range from 5 to 8 GHz.
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