基带
电气工程
电子工程
放大器
电容器
工程类
CMOS芯片
电压
作者
Caroline Andrews,Luke Diamente,Dong Yang,Benjamin C. Johnson,Alyosha Molnar
出处
期刊:IEEE Journal of Solid-state Circuits
[Institute of Electrical and Electronics Engineers]
日期:2013-04-19
卷期号:48 (5): 1188-1198
被引量:37
标识
DOI:10.1109/jssc.2013.2254535
摘要
In this work we present an architecture for a low power SDR which draws on techniques from both narrowband low power radios and recent work in SDRs. The receiver consists of a wide tuning-range passive mixer, driven with resonant non-overlapping LO drive combined with a noise-power optimized multi-path baseband amplifier. LO generation circuitry drives the mixer with an 8-phase, 12.5% duty cycle LO, but does so directly from complementary LC-tank VCOs in order to resonate out the gate capacitance of the mixer. A capacitor sharing technique on the baseband side of the mixer doubles the RX frequency range of the 8-phase clock at no added cost in power or performance, while achieving a NF as low as 7 dB. The 1.8 mW low noise baseband amplifier reuses the bias current of its four input channels while rejecting the 3rd/5th harmonics by >34 dB. The receiver consumes 10–12 mW (including VCOs, pulse generation and baseband) over a frequency range of 0.7–3.2 GHz with a 1.3 V supply.
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