无杂散动态范围
逐次逼近ADC
模数转换器
动态范围
积分非线性
CMOS芯片
线性
微分非线性
电子工程
放大器
总谐波失真
功勋
计算机科学
有效位数
电气工程
物理
电容器
电压基准
电压
工程类
转换器
光电子学
作者
Dong-Ryeol Oh,Kyong Whan Moon,Won-Mook Lim,Ye-Dam Kim,Eun-Ji An,Seung-Tak Ryu
出处
期刊:IEEE Journal of Solid-state Circuits
[Institute of Electrical and Electronics Engineers]
日期:2021-04-01
卷期号:56 (4): 1216-1226
被引量:10
标识
DOI:10.1109/jssc.2020.3044624
摘要
An 8-bit 1-GS/s asynchronous loop-unrolled (LU) successive approximation register (SAR)-Flash hybrid analog-to-digital converter (ADC) with complementary dynamic amplifiers (CDAs) is presented. The proposed ADC is a combination of an asynchronous LU-SAR ADC and a reference-embedding 8 × interpolating flash (I-Flash) ADC to enhance the conversion speed. Operating the CDAs in a dual-edge manner makes it possible to achieve an 8-bit resolution with only four CDAs and one capacitive digital-to-analog converter (C-DAC), which improves the power and area efficiency as well as the input bandwidth. A prototype ADC implemented in a 28-nm CMOS process occupies a 0.002 mm 2 active area. The measured differential non-linearity (DNL) and integral non-linearity (INL) after offset calibration is 0.59 and 0.82 LSB, respectively. With a 0.499-GHz input, the measured signal-to-noise and distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) are 45.5 and 59.4 dB, respectively. The measured effective resolution bandwidth (ERBW) is above 3 GHz. The power consumption at 1-GS/s conversion is 2.55 mW with a supply voltage of 1.1 V, leading to a figure of merit (FoM) of 16.6 fJ/conversion-step.
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