Optimization of the CMP process for direct wafer-to-wafer oxide bonding

Direct wafer-to-wafer oxide bonding is an efficient method for the 3D integration of heterogeneous or homogeneous substrates and occupies a significant place in the advanced packaging technology portfolio. With multiple back-end of the line (BEOL) interconnect metallization layers, complexities in underlying film topologies may translate to significant variations in the surface topology and flatness at the bonding layer. During bonding, such variations can lead to unbonded void defects at the bond interface. For ensuring effective and reliable bonding with minimal defects, surface non-uniformities need to be planarized using a well-controlled chemical mechanical polishing (CMP) process, particularly important for fine-pitch hybrid bonding. In this study, It is demonstrated that CMP is a crucial factor for achieving void-free bonding and the quality of bonding is closely linked to CMP conditions. Systematic investigation has been carried out to improve surface topography on device wafers via CMP process optimization. The results have potential implications for optimizing Cu/dielectric fine-pitch wafer-to-wafer hybrid bonding processes.