A Design and Characterization of CMOS SPAD Fabricated in a 0.18- μ m Standard Process

This article presents the design and characterization of a cost-effective single-photon avalanche diode (SPAD) implemented using a standard 180-nm CMOS process without any process modification. Proposed SPAD employs a p+/n-well junction as the multiplication region and realized in two main structures, where one structure utilizes a deep n-well for vertical isolation and the other employs lateral n-well spacing to form a self-aligned p-well guard-ring. Various substructures are employed, including spacing between two adjacent n-wells, extension of the n-well beyond the deep n-well, presence of a silicide layer, and position of the contact, to investigate their effects on breakdown uniformity, dark count rate (DCR), and photon detection probability (PDP). Electrical characterization, such as current-voltage (I–V) measurement, confirmed possible avalanche behavior with well-defined breakdown voltages, while optical measurements revealed that the non-silicide structure achieved the highest PDP of approximately 10% with an excess bias voltage (V ${}_{\mathbf {EX}}$ ) of 1 V. The light emission test (LET) further verified uniform avalanche activity across the p+/n-well junction, validating the effectiveness of the proposed guard-ring design in suppressing edge-triggered breakdown. These results demonstrate that a fully functional SPAD can be realized within a standard CMOS process, offering a cost-efficient solution for single-photon detection and time-resolved imaging applications.