Signal Margin, Density, and Scalability of 3-D DRAM: A Comparative Study of Two Bitline Architectures

Dynamic random access memory (DRAM) density scaling can be enabled by monolithically stacking DRAM cells in the vertical direction (3-D DRAM). However, there is no analysis of whether 3-D DRAM with horizontal bitline (HBL) or vertical bitline (VBL) is more scalable. Here, we evaluate the signal margin and bitcell density of HBL versus VBL 3-D DRAM using process and circuit simulations, paying attention to the impact of parasitic capacitance. We study the minimum required storage capacitors to provide sufficient signal margin to counterbalance parasitic bitline (BL) capacitance and BL–BL coupling noise. We model three different staircase contact structures and evaluate their impact on bitcell density. To surpass the density of 12-nm 4F $^{\text{2}}$ DRAM while maintaining robust signal margin, VBL 3-D DRAM requires $\sim$ 50 layers, which is 35% fewer than HBL. In addition, we identify VBL 3-D DRAM as a better candidate for future scaling toward short-BL (small storage capacitor) 3-D DRAM using low-leakage access transistors, with up to 4 $\times$ higher density versus 12-nm 2-D DRAM with 128 cells per BL.