A 130–160 GHz Frequency Doubler with Fully Transformer-Based Networks in 40nm Bulk CMOS

To address the area and bandwidth issues of D-band frequency multipliers in CMOS process, this work presents a frequency doubler utilizing fully transformer-based passive networks. The output network overcomes the trapping effect commonly associated with single-ended to single-ended transformers, ensuring broadband output matching. For broadband input and interstage matching, single-ended-to-differential and differential-to-differential transformer-based networks with leakage inductors are implemented. Fabricated using a 40-nm CMOS process, the proposed frequency doubler features a compact total area of 0.17 mm- and a core area of 0.06 mm², with a measured 3-dB bandwidth from 130 to 160 GHz and an in-band fundamental rejection ratio exceeding 26 dBc.