Numerical Study of Two-Phase Immersion Cooling Limits for Bare Die Packages With Novec 649

Abstract As chip power densities continue to increase, there is renewed interest in using two-phase immersion cooling (2PIC) as a passive thermal management mechanism to improve data center power density and operating efficiency. Traditional air cooling approaches are challenging to scale for high power chips due to costly requirements on cooling footprint, fan power, and increasingly untenable levels of acoustic noise. Single-phase liquid cooling can address some of these challenges but requires the introduction of complex fluid delivery manifolds, cold-plate loops and active pumps. In this study, we use a semi-empirical, numerical approach to investigate two-phase immersion cooling limits for bare die packages with Novec 649, a low global warming potential (GWP) coolant. This simplified modeling method enables rapid parametric studies to extract relevant 2PIC thermal system design information without requiring experimental tanks or computationally expensive two-phase simulations. From the results, we identify 2PIC thermal design power limits for bare die packages of various sizes with different distributions of heat sources and different boiler plate designs. We also identify key contributors to the 2PIC thermal resistance stack up and provide recommendations on potential improvements to overall junction to fluid resistance. Finally, we compare the 2PIC results against a single-phase, water-cooled coldplate case study and discuss pros and cons of both.