Digital Circuit Performance Evaluation of Parallel Gated Junctionless Field Effect Transistor

This paper reports the modeling and performance enhancement of complementary metal-oxide-semiconductor (CMOS) inverters using parallel-gated junctionless field-effect transistors (PGJLFET). A mathematical model for different parameters, namely, low and high input voltage, low and high output voltage, noise margin, rise time, fall time, propagation delay, and power dissipation of the inverter circuit was established. To establish the model for various parameters, potential models at the source-channel boundary and the potential at the drain-channel boundary are considered. The variations in the voltage transfer characteristics of the output current with respect to the input voltage and the power dissipation with respect to the input voltage for steady-state conditions and transient states were investigated for different gate dielectrics, gap lengths, and gate oxide thicknesses. The models were validated by comparing them with technology computer-aided design (TCAD) simulation results. The noise margin, rise time, fall time, and propagation delay of the PGJLFET-based inverter are estimated and compared with those of a conventional junctionless transistor. It has been observed that the PGJLFET exhibits an improvement in the noise margin and propagation delay compared with conventional junctionless transistors.