Wafer level packaging (WLP): Fan-in, fan-out and three-dimensional integration

In this paper, the state-of-the-art results of research and development in wafer-level packaging (WLP) is reviewed. The paper starts from the introduction of several fan-in wafer-level packaging technologies. The focus is given on the fan-in WLP reliability performance as related to the structural differences. New failure mechanisms that appear in build-up stack layers are discussed. Next, emerging fan-out wafer level packaging technologies are introduced. Several key challenges in fan-out WLP technologies are examined. Finally, Three-dimensional (3-D) integration of through-silicon-via (TSV) technology and wafer-level bonding technology with WLP, especially in MEMS and image sensor applications, is discussed.