Investigation of poly-Si/HfO/sub 2/ gate stacks in a self-aligned 70nm MOS process flow

NMOS and PMOS transistors with poly-Si gate electrode and HfO/sub 2/ gate dielectric were fabricated using a conventional self-aligned process flow. Functional transistors with final EOT/spl sim/1.8 nm were obtained down to 70 nm gate lengths using a low thermal budget process without a poly re-oxidation step. Electrical data and TEM analysis indicate that lateral oxygen diffusion was not an issue in EOT degradation. An asymmetric V/sub FB/ shift is observed for NMOS and PMOS transistors. The drive current for transistors with a high-k gate dielectric is improved by 10-15% with gate length scaling, but even for 70 nm gate length transistors it reaches only 60% of the SiON currents.