A 0.52pJ/bit 0.448Tbps/mm UCIe Standard Package Die-to-Die Transceiver with Low-Latency TX Clock Alignment in 3nm FinFET

This work presents a UCIe SP compliant die-to-die wireline transceiver developed in a 3nm CMOS process node. Each 16-lane module operates at 16Gbps/pin yielding a 0.448Tbps/mm beachfront bandwidth while only consuming 0.52pJ/bit. A TX clock alignment scheme implements clock domain crossing to reduce the FDI-to-FDI latency to 4.0ns. With a 25mm organic substrate channel, an aggregate 0.372UI eye opening at BER of le-15 and 0.108UI at BER of le-27 is measured at 16Gbps/pin operation. A background maintenance mode improves the aggregate eye width by up to 0.156UI across +5% to −5% voltage and −40C to 125C temperature drift.