Through-chip porous layer fabrication by plasma etching with protective film deposition

We developed a process for fabricating through-chip porous layers using porous Si formed on a crystalline Si substrate. In micronano systems, porous materials are expected to perform various functions. We have utilized porous Pt layers obtained from porous Si as the catalyst layers in miniature fuel cells. Recently, to explore novel functions, we attempted to fabricate through-chip porous Au layers. Unlike Pt, porous Au layers are rapidly etched during plasma etching, making it extremely difficult to achieve a through-chip porous Au layer. In this study, we explored the incorporation of protective film deposition into the etching process, which is similar to deep reactive ion etching. Because of the large surface area of the porous regions, the amount of protective film components deposited on the porous layer may be larger than that on the bulk regions, potentially leading to a reversal in the etching rate, where the porous regions are etched slower than the bulk regions. The plasma process alternating protective film deposition and etching was performed using a parallel plate reactive ion etching system, and conditions were identified under which the etching rate of porous Si is lower than that of bulk Si. Using these conditions, we successfully fabricated through-chip porous Au layers over a wide area.