Exploration and Analysis of Through-Glass Vias for High-Speed, Low-Loss Vertical Interconnects in Glass-Based 3-D Integrated Circuits

In glass-based 3-D integrated circuits (ICs), nonuniform through-glass vias (TGVs) contribute to increased delay, higher losses, and performance degradation, particularly notable in dense multilayer stacked circuits operating at high frequencies. To explore high-speed, low-loss vertical interconnections, we develop nonuniform TGVs double-layer vertical interconnect models and analyze impedance, insertion loss, and delay across various taper and sidewall roughness configurations. This study confirms a positive correlation among sidewall roughness, taper, and both loss and signal delay. Detailed examination of Smith charts for double-layer vertically interconnected TGVs further illustrates worsening impedance matching with increasing sidewall roughness and taper. In addition, we extract parasitic RLGC parameters, revealing that increased taper exacerbates parasitic effects induced by sidewall roughness, providing evidence for observed losses and delays. Our findings underscore the superior performance of cylindrical TGVs, advocating smaller taper and lower sidewall roughness for enhanced microwave performance in multilayer vertically interconnected devices. Experimental validation supports our conclusions, with measured results aligning well with simulations up to 40 GHz. Moreover, increased multilayer misalignment is confirmed to correlate with higher signal transmission loss and delay, while the loss positively correlates with the radius of pads between interconnection layers.