Single-Mode CMOS 6T-SRAM Macros With Keeper-Loading-Free Peripherals and Row-Separate Dynamic Body Bias Achieving 2.53fW/bit Leakage for AIoT Sensing Platforms

Miniaturized wireless IoT sensor nodes stay mostly in their standby mode and wake up periodically to sense and store a small amount of data. To maximize battery life, the acquired data is usually accumulated in SRAM before being transmitted; requiring economic on-chip memory solutions with ultra-low standby power. Artificial-intelligence-of-things (AIoT) based sensing platforms aim to extend this concept further by using on-chip neural networks (NN) to detect valid events at the edge node; further reducing network traffic and overall power consumption by limiting the transmission of invalid events [1]. This edge intelligence has created an ever-increasing demand for on-chip SRAM: high capacity is required to store a large number of weights and accumulated features for accurate decisions; low leakage is critical for data retention as the edge nodes stay in standby for the majority of time; speed is important to deliver timely processing and fast propagation of emergent events; and area, as well as technology availability, are keys to keep the cost down. It is also preferred not to use a dedicated retention mode to eliminate the latency and power overhead of mode switching, which is more frequent when working with light and sparse data traffic in AIoT sensing scenarios.